A semiconductor integrated circuit (“IC”) is generally susceptible to an electrostatic discharge (“ESD”) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration, during which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event. Examples of known ESD protection schemes are shown in FIGS. 1 and 2.
In deep-submicron complementary metal-oxide semiconductor (“CMOS”) process technology with shallow-trench isolations (“STIs”), a silicon controlled rectifier (“SCR”) has been used for ESD protection. A feature of an SCR is its voltage-holding ability. An SCR can sustain high current and hold the voltage across the SCR at a low level, and may be implemented to bypass high-current discharges associated with an ESD event.
FIG. 1 is a reproduction of FIG. 3 of U.S. Pat. No. 5,012,317 to Rountre, entitled “Electrostatic Discharge Protection Circuit.” Rountre describes a lateral SCR structure made up of a P+ type region 48, an N-type well 46, a P-type layer 44, and an N+ region 52. According to Rountre, a positive current associated with an ESD event flows through region 48 to avalanche a PN junction between well 46 and layer 44. The current then flows from layer 44 to region 52 across the PN junction and ultimately to ground, to protect an IC from the ESD event. However, a disadvantage of the SCR structure shown in FIG. 1 is its susceptibility to being accidently triggered by a substrate noise, resulting in device latch-up.
FIG. 2 is a reproduction of FIG. 5 of U.S. Pat. No. 6,258,634 (the '634 patent) to Wang, entitled “Method for Manufacturing a Dual-Directional Over-Voltage and Over-Current Protection Device and Its Cell Structure.” The '634 patent describes a two-terminal ESD protection structure providing protection against both positive and negative ESD pulses that may appear across an anode A and a cathode K. When a positive pulse is applied across terminals A and K, transistors 140 and 150 turn on. Thereafter SCR 170, defined by p-n-p-n regions 114, 116, 118 and 120, is triggered into a snap-back mode. Alternatively, when a negative pulse is applied between terminals A and K, transistors 140 and 130 turn on. Subsequently, SCR 180, defined by p-n-p-n regions 118, 116, 114 and 112, is triggered into a snap-back mode. The triggering of SCR 170 or SCR 180 into a snap-back mode results in the formation of a very low impedance path between terminals A and K to discharge the ESD current. FIG. 3, a reproduction of FIG. 6 of the '634 patent, shows the current-voltage characteristic of the ESD protection structure disclosed in the '634 patent. However, the structure is formed inside a silicon substrate with a deep n-well, and therefore must be manufactured by a mixed-mode CMOS process that supports a deep n-well fabrication processing step, rather than a general CMOS process.